1. Field of the Invention
The present invention relates to a band-gap reference circuit. In particular, it relates to a band-gap reference circuit with a start-up circuit attached.
2. Description of the Related Art
Japanese Patent Application Laid-open No. Hei 8-186484 discloses a band-gap reference circuit containing a start-up circuit, which is used to reduce the amount of time that elapses from when the power source voltage is first supplied until a stable operating state is attained in the band-gap reference circuit, which generates a stable (in terms of temperature change), predetermined standard voltage and which operates basically in the PN junction band-gap region. FIG. 1 shows the conventional circuit disclosed in Japanese Patent Application Laid-open No. Hei 8-186484.
The conventional band-gap reference circuit is comprised of a band-gap circuit 10, which generates and outputs the pre-determined, standard voltage VREF during the active state; and a start-up circuit 20, which reduces the time elapsing from when the power source is first applied up to it reaching a stable operating state.
Band-gap circuit 10 is comprised of P-channel MOS transistor (PMOS) 11, which has its source connected to power source VDD (the high voltage side) and has its gate and drain connected to each other and also connected to node A; N-channel MOS transistor (NMOS) 12, which has its drain connected to the drain of PMOS 11; first resistor 13, which has one terminal connected to the source of NMOS 12 and the other terminal connected to the ground (the low voltage side of the power source); PMOS 14, which has its source connected to power source VDD and its gate connected to the drain of PMOS 11; and NMOS 15, which has its drain connected to its gate, and to the drain of PMOS 14 and gate of NMOS 12 and also connected to node B, and which has its source connected to the ground. Band-gap circuit 10 is further comprised of PMOS 16, which has its source connected to power source VDD, its gate to node A, and has its drain as a standard voltage output terminal; second resistor 17, which has one terminal connected to the drain of PMOS 16; and diode 18, which has its anode connected to the other terminal of second resistor 17 and its cathode connected to the ground.
According to the Japanese Patent Application Laid-open Hei 8-186484 mentioned above, the reference voltage output VREF when band-gap circuit 10 is in a stable operating state can be given as the following equation:
VREF=Nxc2x7(kxc2x7T/q)xc2x7ln M+VFxe2x80x83xe2x80x83(1)
where N is the ratio of the resistance value of the first resistor 13 over the resistance value of the second resistor 17; k is Boltzmann constant; T is absolute temperature; q is the electron charge; M is the ratio of the gate width of NMOS 12 over the gate width of NMOS 15; VF is the forward bias across diode 18. In order to prevent an occurrence of changes in the characteristics of each transistor due to manufacturing irregularities, the each respective channel length of PMOS 11, PMOS 14, PMOS 16, NMOS 12, and NMOS 15 should be at least 10 xcexcm, with the range of 50 xcexcm to 100 xcexcm being most preferable.
Start-up circuit 20 is made up of PMOS 21, which has its source connected to power source VDD; PMOS 22, which has its source also connected to power source VDD, and which also has its gate connected to the drain of PMOS 21 forming node C; third resistor 23, which has one terminal connected to node C and the other terminal connected to the ground; and capacitor 24, which has one terminal connected to node C and the other terminal connected to the ground. Signal S1 output from node A of band-gap circuit 10 is input to the gate of PMOS 21, and the drain of PMOS 22 is connected to node B in band-gap circuit 10.
FIG. 2 is an operational timing graph for the conventional circuit at the time when power is first supplied. The workings of the conventional band-gap reference circuit at the time when power is first applied will now be described in detail while referencing FIG. 2.
As shown in FIG. 2, it is assumed that power source voltage VDD starts at nearly 0 V climbing up to 3.3 V. When power source voltage VDD is first supplied, which is shown in FIG. 2 as the time-frame from time-point t1 to t2, since the source of PMOS 11 is the voltage level equal to VDD and its gate is nearly ground level (0 V), the voltage difference between the gate and source of PMOS 11 is smaller than its threshold voltage Vtp1 of PMOS 11 in terms of their absolute values. This causes the transistor to turn off. Also, since the voltage levels at the source and gate of PMOS 21 are the same as the respective voltage levels at the source and gate of PMOS 11, PMOS 21 is also turned off and accordingly, node C is at ground level.
When power source voltage VDD continues to appreciate past time-point t2, the voltage difference between the gate and source of PMOS 11 becomes larger than the threshold voltage Vtp1 of PMOS 11 in terms of their absolute values. This causes PMOS 11 to turn on, and node A rises keeping pace with power source voltage VDD, while maintaining a difference of roughly Vtp1 lower than VDD. In the same manner, when PMOS 21 is also turned on, the voltage level at node C in start-up circuit 20 begins to appreciate at a remarkably slow rate when compared to the rise in the power source level VDD due to resistor 23 and capacitor 24.
At this point, when all of the PMOS transistors in both band-gap circuit 10 and start-up circuit 20 have the same channel lengths and the same threshold voltage Vtp1, if the voltage difference between the power source voltage VDD and node C continues to become larger than Vtp1, in terms of their absolute values, past time-point t2, then the charging of node B is accelerated because PMOS 22 will also be turned on.
At time-point t3, due to the rising voltage level at node B, the gate voltage of NMOS 12 and NMOS 15 surpasses the threshold voltage Vtn and they are turned on. As a result, the increase in voltage level at node A temporarily stagnates. Accordingly, the difference between the voltage levels of the gate and source of PMOS 21 surges, turning PMOS 21 on deeply. Moreover, because the PMOS transistor being utilized for PMOS 21 has an extremely large channel width that is hundreds of times larger than that of PMOS 11, at time-point t4 the voltage level of node C comes under the influence of power source voltage VDD and begins a rapid ascent. Then since PMOS 22 turns off as the voltage level of node C approaches that of power source voltage VDD, start-up circuit 20 becomes electrically isolated from band-gap circuit 10. Once power source voltage VDD stabilizes at its predetermined voltage level (e.g., 3.3 V in FIG. 2), terminals A and B of band-gap circuit 10, as well as output reference voltage VREF stabilize at their respective pre-determined voltages.
With the band-gap reference circuit with an attached start-up circuit as shown in FIG. 1, when power source voltage VDD is first applied, node B in band-gap circuit 10 momentarily has more charge than start-up circuit 20. As a result, it is possible for a band-gap circuit without the start-up circuit to reach its stable state in a very short time compared to when node B is charged with only the very small amount of current flowing through PMOS 14.
In this conventional band-gap reference circuit, however, the start-up circuit requires an enormous amount of exclusive space since the channel width of PMOS 21 within the start-up circuit must be large, and demands have been made for a reduction in this required surface area. In accordance with these demands, if the channel length of PMOS 21 is reduced by a factor of 1/n compared to the other PMOS transistors then it is possible to reduce the channel width by the same factor of 1/n; therefore the required space for the gate is able to be reduced by a factor of 1/(n+n), but unfortunately when it was tested it became apparent that a new problem had developed.
During testing, a band-gap reference circuit was formed with the PMOS 21 shown in FIG. 1 having a channel width made to be 0.35 xcexcm and the channel width of the other PMOS transistors made to be 80 xcexcm. The power source voltage VDD was reduced from 3.3 V to 0.6 V, then after being held at 0.6 V for a period of 500 ms, re-powered up to reach the voltage level of 3.3 V. When the time required for the reference voltage output VREF to reach the predetermined voltage level and stabilize was measured, it was found that the band-gap reference circuit containing the PMOS 21 with a channel length shortened to 0.35 xcexcm required an inordinate amount of time to stabilize at output reference voltage VREF. The following has been devised in order to rectify the cause of this new problem.
In the band-gap reference circuit that was tested, and which had the structure shown in FIG. 1, threshold voltage Vtp1 of PMOS 11, PMOS 14, PMOS 16, and PMOS 22, which all have 80 xcexcm channel lengths, was xe2x88x920.9 V, and threshold voltage Vtp2 of PMOS 21, which has a 0.35 xcexcm channel length, was xe2x88x920.5V. This reduction in threshold voltage was found to be the cause of the short channel effect.
When the power source voltage VDD is reduced to 0.6 V, PMOS 11 has high impedance. This causes node A to be nearly 0 V. On the other hand, since the threshold voltage of PMOS 21 is xe2x88x920.5V, it maintains an on state. For this reason, when the power source voltage VDD starts increasing from 0.6 V, the voltage level of node C increases in tandem with power source voltage VDD. Accordingly, since the voltage levels at the gate and source of PMOS 22 are both equal to the power source voltage VDD, PMOS 22 stays turned off and does not turn on, which means that the start-up circuit 20 does not operate properly. Therefore the band-gap circuit 10 operates as if the start-up circuit 20 did not exist; in other words, node B is charged solely by the very small amount of electrical current flowing through PMOS 14. It is because of this electric gain at node B being so slow that the voltage levels of the gates in neither NMOS 12 nor NMOS 15 reach their respective threshold voltage Vtn, and thereby begin to operate in the weak inversion region, and as a result cause the band-gap circuit 10 to require an inordinate amount of time to stabilize.
As it has been described above, since the area occupied by PMOS 21, which charges node C within the start-up circuit, is large in the conventional band-gap reference circuit; it restricts possible reductions in the size of the entire band-gap reference circuit. Furthermore, when the channel length of PMOS 21 is shortened in order to reduce the size of the area it occupies, due to the lowest level reached by power source voltage VDD during a short transmission interruption, the start-up circuit may not be able to operate properly.
The objective of the present invention is to provide a band-gap reference circuit in which the area occupied by PMOS 21 is reduced, thereby reducing the total occupied area of the entire band-gap reference circuit, and one that can start-up properly without regard to how many volts the lowest level reached by power source voltage VDD is during a short transmission interruption.
According to an aspect of the present invention, a band-gap reference circuit (20, 30, 10), which generates and supplies a predetermined stable voltage (VREF), is provided. The band-gap reference circuit is comprised of a start-up circuit (20), which is comprised of a start-up transistor (21a) that is smaller than each of those in a band-gap circuit (10) which generates a predetermined stable voltage and which outputs a start signal (S1); and a signal level converter (30), which converts said start signal (S1) to a second start signal (S2) that is supplied to said start-up transistor (21a). An example of this band-gap reference circuit is illustrated in FIGS. 3 and 5.